Htydjtk

According to https://en.wikipedia.org/wiki/Cray-1

The Cray-1 was built as a 64-bit system, a departure from the 7600/6600, which were 60-bit machines (a change was also planned for the 8600). Addressing was 24-bit, with a maximum of 1,048,576 64-bit words (1 megaword) of main memory, where each word also had 8 parity bits for a total of 72 bits per word.[10] There were 64 data bits and 8 check bits.

It seems to me by the nature of parity, it should suffice to have one bit of overhead per word, rather than eight. I can understand on something like an 8088/87, you might be stuck with 1/8 because the memory system deals in eight bits at a time, but why is it that way on a 64-bit machine?

There were 64 data bits and 8 check bits.

It seems to me by the nature of parity, it should suffice to have one bit of overhead per word, rather than eight. [...]

What you refer to here is a simple single bit parity. Basically counting the number of ones (even parity) or zeros (odd). Such a mechanism can only detect an odd number of bit flips (1 or 3 or 5 or ... flipping). Even numbers of flips can't be detected and will result in undetected computing errors.

What the Cray uses is a parity system based on Hamming encoding. Encoding parity this way allows detection of multiple bit errors within a word and even correction of these on the fly. The 8-bit code used was able to correct single bit errors (SEC) and detect double error (DED).

So while a machine with a single bit parity can detect single bit flips, it will always fail on double flips. Further, even if an error is detected, the only solution is to halt the program. With SEC-DED, a single error detected will be recovered (final) on the fly (at cost of maybe a few cycles) and a multi-bit error will halt the machine.

I can understand on something like an 8088/87, you might be stuck with 1/8 because the memory system deals in eight bits at a time, but why is it that way on a 64-bit machine?

Because it's still just 1/8th, but now with improved flavour :))

Considering the quite important function of invisible error correction, the question is rather why only 8. Longer codes would allow to detect even longer errors and multi-bit corrections. With the 1 Ki by 1 RAMs used (Fairchild 10415FC), any width could have been made. Then again, while the Cray 1 architecture shows a switch to the 'new' standard of 8 bit units - so using 8 parity bits comes naturally. Doesn't it?

Remark#1

Eventually it's the same development the PC took, just instead of going from 9 bit memory (SIMM) over 36 bit (PS/2) to today's 72 Bit DIMM, the Cray-1 leapfrogged all of this and started with 72 Bit right away.

Remark#2

Seymour Cray is known to have said that 'Parity is for Farmers' when designing the 6600. While this quote was famous in inspiring the reply 'Farmers buy Computers' when parity got introduced with the 7600, not may know what he was referring to on an implied level: The Doctrine of Parity, a US policy to make farming profitable again during and after the great depression - a policy that to some degree still results in higher food prices in the US than in most other countries.

Remark#3

The Cray Y-MP of 1990 even went a step further and added parity to (most) registers. Also the code was changed to enable double-bit correction and multi-bit detection.

After the first Cray-1 was built, some calculation determined that the time between failures would be greatly extended by having a single-error-correction-double-error-detection (SECDED) without much cost in speed. The point is that with large memory, random single bit errors occur every few hours; with SECDED, it's every few years or so.

The extra bits are used to allow for error detection and correction (EDAC).

This scheme is described in detail in: Cray 1 Hardware Reference Manual at page 5-5 (~168)

The use of EDAC in the Cray-1 is rather ironic given that Seymour Cray is (in)famous for once saying

Parity is for farmers.

Which I think is a reference to farm subsides in Europe.