What were wait-states, and why was it only an issue for PCs?
PC compatibles in the 1980s were often advertised as having zero, one, two, or sometimes more "wait states". Zero wait states was the best.
Basically, the wait-states I am asking about are due to the main system DRAM being too slow for the CPU, so extra bus cycles were added to make up for this latency. This reduced the overall processing speed.
I'm not asking about cases where a CPU is blocked from accessing main system RAM by some peripheral doing DMA, for example. Obviously, that's a feature for improving performance.
But I don't recall this being an issue on comparatively-priced machines with 16 or 32-bit Motorola processors, and running at similar clock speeds.
What was the cause of the wait states, precisely, and how come other low-cost home computers were able to avoid this performance problem?
ibm-pc memory
add a comment |
PC compatibles in the 1980s were often advertised as having zero, one, two, or sometimes more "wait states". Zero wait states was the best.
Basically, the wait-states I am asking about are due to the main system DRAM being too slow for the CPU, so extra bus cycles were added to make up for this latency. This reduced the overall processing speed.
I'm not asking about cases where a CPU is blocked from accessing main system RAM by some peripheral doing DMA, for example. Obviously, that's a feature for improving performance.
But I don't recall this being an issue on comparatively-priced machines with 16 or 32-bit Motorola processors, and running at similar clock speeds.
What was the cause of the wait states, precisely, and how come other low-cost home computers were able to avoid this performance problem?
ibm-pc memory
1
Brian, this question is rather wide. It's almost like asking why TTL chips need current and why don't they use all the same. It might be a good idea to narrow it a bit down.
– Raffzahn
2 hours ago
Many processors have had some notion of variable memory timing that can be configured one way or another. Some dynamically, some by data driven configuration, others by simply hard-coding one specific timing. See, for example, retrocomputing.stackexchange.com/questions/9562/…
– Erik Eidt
1 hour ago
add a comment |
PC compatibles in the 1980s were often advertised as having zero, one, two, or sometimes more "wait states". Zero wait states was the best.
Basically, the wait-states I am asking about are due to the main system DRAM being too slow for the CPU, so extra bus cycles were added to make up for this latency. This reduced the overall processing speed.
I'm not asking about cases where a CPU is blocked from accessing main system RAM by some peripheral doing DMA, for example. Obviously, that's a feature for improving performance.
But I don't recall this being an issue on comparatively-priced machines with 16 or 32-bit Motorola processors, and running at similar clock speeds.
What was the cause of the wait states, precisely, and how come other low-cost home computers were able to avoid this performance problem?
ibm-pc memory
PC compatibles in the 1980s were often advertised as having zero, one, two, or sometimes more "wait states". Zero wait states was the best.
Basically, the wait-states I am asking about are due to the main system DRAM being too slow for the CPU, so extra bus cycles were added to make up for this latency. This reduced the overall processing speed.
I'm not asking about cases where a CPU is blocked from accessing main system RAM by some peripheral doing DMA, for example. Obviously, that's a feature for improving performance.
But I don't recall this being an issue on comparatively-priced machines with 16 or 32-bit Motorola processors, and running at similar clock speeds.
What was the cause of the wait states, precisely, and how come other low-cost home computers were able to avoid this performance problem?
ibm-pc memory
ibm-pc memory
edited 1 hour ago
Brian H
asked 2 hours ago
Brian HBrian H
18k67154
18k67154
1
Brian, this question is rather wide. It's almost like asking why TTL chips need current and why don't they use all the same. It might be a good idea to narrow it a bit down.
– Raffzahn
2 hours ago
Many processors have had some notion of variable memory timing that can be configured one way or another. Some dynamically, some by data driven configuration, others by simply hard-coding one specific timing. See, for example, retrocomputing.stackexchange.com/questions/9562/…
– Erik Eidt
1 hour ago
add a comment |
1
Brian, this question is rather wide. It's almost like asking why TTL chips need current and why don't they use all the same. It might be a good idea to narrow it a bit down.
– Raffzahn
2 hours ago
Many processors have had some notion of variable memory timing that can be configured one way or another. Some dynamically, some by data driven configuration, others by simply hard-coding one specific timing. See, for example, retrocomputing.stackexchange.com/questions/9562/…
– Erik Eidt
1 hour ago
1
1
Brian, this question is rather wide. It's almost like asking why TTL chips need current and why don't they use all the same. It might be a good idea to narrow it a bit down.
– Raffzahn
2 hours ago
Brian, this question is rather wide. It's almost like asking why TTL chips need current and why don't they use all the same. It might be a good idea to narrow it a bit down.
– Raffzahn
2 hours ago
Many processors have had some notion of variable memory timing that can be configured one way or another. Some dynamically, some by data driven configuration, others by simply hard-coding one specific timing. See, for example, retrocomputing.stackexchange.com/questions/9562/…
– Erik Eidt
1 hour ago
Many processors have had some notion of variable memory timing that can be configured one way or another. Some dynamically, some by data driven configuration, others by simply hard-coding one specific timing. See, for example, retrocomputing.stackexchange.com/questions/9562/…
– Erik Eidt
1 hour ago
add a comment |
2 Answers
2
active
oldest
votes
It was an issue on all machines — wait states resolve any situation in which the part a processor needs a response from isn't yet ready to respond — but only in the commoditised world of the PC was it a variable and therefore worth putting in the advertising.
In the Atari ST, wait states are inserted if the 68000 tries to access RAM during a video slot (two of every four cycles), or when it accesses some peripherals (e.g. there is a fixed one-cycle delay for accessing the sound chip).
The Amiga differentiates chip RAM and fast RAM. Chip RAM is that shared with the coprocessors and in which the CPU may encounter wait states. Small Amigas like the unexpanded A600 have only chip RAM.
Conversely, on the PC processors scaled in processing speed much more widely, the underlying reasons for potential waits were much more variable, and one manufacturer would likely do a better job than another. So it warranted boasting about if your machine has a good number rather than a bad one.
I was referring to wait states introduced by DRAM latency, not contention with DMA devices sharing the bus. I'll try to clarify...
– Brian H
1 hour ago
It wasn't an issue with all machines, but it was an issue which spread across many types of machines. On something like a VIC-20 or an Apple II, the memory system will always respond to a request by the time the CPU would be interested in the response. Conversely, on something like a 6502-based Nibbler arcade machine, ROM accesses were designed to have a wait state (although a machine used in competition had a broken wait-state circuit whose failure simply caused the game to run a little faster than normal, giving the player an unfair advantage).
– supercat
57 mins ago
There's an obvious reason for that, in that the Apple II and VIC-20 have CPUs running at 1MHz, while the RAM is faster. As such the CPU can access the RAM on without any wait states; it's even fast enough for the video hardware to have a go on alternate cycles usually without contention. Once you've got a CPU that's faster than its RAM, wait states are inevitable though.
– Matthew Barber
50 mins ago
There are small machines with wait states induced only by slow RAM — e.g. the Electron accesses ROM at 2Mhz but RAM at a max 1Mhz and forces delays to the CPU to deal with the latter. Does that count?
– Tommy
15 mins ago
add a comment |
The DRAM chips used for memory needed a certain memory access cycle length, for example 1000ns. Also CPUs needed several clock cycles to perform a memory cycle, so for example a 8086 could take 4 cycles to access memory. If the CPU is running at 5 MHz, the memory access takes only 800ns which is too fast for the memory. Therefore one wait state is needed to get 1000ns memory cycle. Lowering the CPU speed to 4 MHz would allow it to run with zero wait states. Basically wait states were needed because memory speeds were slower than what CPUs could access. Advertising does tell something about system performance. For example, if one system has 1000ns memories and another has 800ns memories, a 5 MHz 8086 is able to run at 0ws with faster memories and at 1ws with slower ones. In theory the 0ws machine can transfer data 25% more in same time than the 1ws machine can. Surely faster memories were more expensive so maybe it was important to advertise why two identical looking systems had a significant price difference.
add a comment |
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2 Answers
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2 Answers
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It was an issue on all machines — wait states resolve any situation in which the part a processor needs a response from isn't yet ready to respond — but only in the commoditised world of the PC was it a variable and therefore worth putting in the advertising.
In the Atari ST, wait states are inserted if the 68000 tries to access RAM during a video slot (two of every four cycles), or when it accesses some peripherals (e.g. there is a fixed one-cycle delay for accessing the sound chip).
The Amiga differentiates chip RAM and fast RAM. Chip RAM is that shared with the coprocessors and in which the CPU may encounter wait states. Small Amigas like the unexpanded A600 have only chip RAM.
Conversely, on the PC processors scaled in processing speed much more widely, the underlying reasons for potential waits were much more variable, and one manufacturer would likely do a better job than another. So it warranted boasting about if your machine has a good number rather than a bad one.
I was referring to wait states introduced by DRAM latency, not contention with DMA devices sharing the bus. I'll try to clarify...
– Brian H
1 hour ago
It wasn't an issue with all machines, but it was an issue which spread across many types of machines. On something like a VIC-20 or an Apple II, the memory system will always respond to a request by the time the CPU would be interested in the response. Conversely, on something like a 6502-based Nibbler arcade machine, ROM accesses were designed to have a wait state (although a machine used in competition had a broken wait-state circuit whose failure simply caused the game to run a little faster than normal, giving the player an unfair advantage).
– supercat
57 mins ago
There's an obvious reason for that, in that the Apple II and VIC-20 have CPUs running at 1MHz, while the RAM is faster. As such the CPU can access the RAM on without any wait states; it's even fast enough for the video hardware to have a go on alternate cycles usually without contention. Once you've got a CPU that's faster than its RAM, wait states are inevitable though.
– Matthew Barber
50 mins ago
There are small machines with wait states induced only by slow RAM — e.g. the Electron accesses ROM at 2Mhz but RAM at a max 1Mhz and forces delays to the CPU to deal with the latter. Does that count?
– Tommy
15 mins ago
add a comment |
It was an issue on all machines — wait states resolve any situation in which the part a processor needs a response from isn't yet ready to respond — but only in the commoditised world of the PC was it a variable and therefore worth putting in the advertising.
In the Atari ST, wait states are inserted if the 68000 tries to access RAM during a video slot (two of every four cycles), or when it accesses some peripherals (e.g. there is a fixed one-cycle delay for accessing the sound chip).
The Amiga differentiates chip RAM and fast RAM. Chip RAM is that shared with the coprocessors and in which the CPU may encounter wait states. Small Amigas like the unexpanded A600 have only chip RAM.
Conversely, on the PC processors scaled in processing speed much more widely, the underlying reasons for potential waits were much more variable, and one manufacturer would likely do a better job than another. So it warranted boasting about if your machine has a good number rather than a bad one.
I was referring to wait states introduced by DRAM latency, not contention with DMA devices sharing the bus. I'll try to clarify...
– Brian H
1 hour ago
It wasn't an issue with all machines, but it was an issue which spread across many types of machines. On something like a VIC-20 or an Apple II, the memory system will always respond to a request by the time the CPU would be interested in the response. Conversely, on something like a 6502-based Nibbler arcade machine, ROM accesses were designed to have a wait state (although a machine used in competition had a broken wait-state circuit whose failure simply caused the game to run a little faster than normal, giving the player an unfair advantage).
– supercat
57 mins ago
There's an obvious reason for that, in that the Apple II and VIC-20 have CPUs running at 1MHz, while the RAM is faster. As such the CPU can access the RAM on without any wait states; it's even fast enough for the video hardware to have a go on alternate cycles usually without contention. Once you've got a CPU that's faster than its RAM, wait states are inevitable though.
– Matthew Barber
50 mins ago
There are small machines with wait states induced only by slow RAM — e.g. the Electron accesses ROM at 2Mhz but RAM at a max 1Mhz and forces delays to the CPU to deal with the latter. Does that count?
– Tommy
15 mins ago
add a comment |
It was an issue on all machines — wait states resolve any situation in which the part a processor needs a response from isn't yet ready to respond — but only in the commoditised world of the PC was it a variable and therefore worth putting in the advertising.
In the Atari ST, wait states are inserted if the 68000 tries to access RAM during a video slot (two of every four cycles), or when it accesses some peripherals (e.g. there is a fixed one-cycle delay for accessing the sound chip).
The Amiga differentiates chip RAM and fast RAM. Chip RAM is that shared with the coprocessors and in which the CPU may encounter wait states. Small Amigas like the unexpanded A600 have only chip RAM.
Conversely, on the PC processors scaled in processing speed much more widely, the underlying reasons for potential waits were much more variable, and one manufacturer would likely do a better job than another. So it warranted boasting about if your machine has a good number rather than a bad one.
It was an issue on all machines — wait states resolve any situation in which the part a processor needs a response from isn't yet ready to respond — but only in the commoditised world of the PC was it a variable and therefore worth putting in the advertising.
In the Atari ST, wait states are inserted if the 68000 tries to access RAM during a video slot (two of every four cycles), or when it accesses some peripherals (e.g. there is a fixed one-cycle delay for accessing the sound chip).
The Amiga differentiates chip RAM and fast RAM. Chip RAM is that shared with the coprocessors and in which the CPU may encounter wait states. Small Amigas like the unexpanded A600 have only chip RAM.
Conversely, on the PC processors scaled in processing speed much more widely, the underlying reasons for potential waits were much more variable, and one manufacturer would likely do a better job than another. So it warranted boasting about if your machine has a good number rather than a bad one.
answered 1 hour ago
TommyTommy
16.3k14780
16.3k14780
I was referring to wait states introduced by DRAM latency, not contention with DMA devices sharing the bus. I'll try to clarify...
– Brian H
1 hour ago
It wasn't an issue with all machines, but it was an issue which spread across many types of machines. On something like a VIC-20 or an Apple II, the memory system will always respond to a request by the time the CPU would be interested in the response. Conversely, on something like a 6502-based Nibbler arcade machine, ROM accesses were designed to have a wait state (although a machine used in competition had a broken wait-state circuit whose failure simply caused the game to run a little faster than normal, giving the player an unfair advantage).
– supercat
57 mins ago
There's an obvious reason for that, in that the Apple II and VIC-20 have CPUs running at 1MHz, while the RAM is faster. As such the CPU can access the RAM on without any wait states; it's even fast enough for the video hardware to have a go on alternate cycles usually without contention. Once you've got a CPU that's faster than its RAM, wait states are inevitable though.
– Matthew Barber
50 mins ago
There are small machines with wait states induced only by slow RAM — e.g. the Electron accesses ROM at 2Mhz but RAM at a max 1Mhz and forces delays to the CPU to deal with the latter. Does that count?
– Tommy
15 mins ago
add a comment |
I was referring to wait states introduced by DRAM latency, not contention with DMA devices sharing the bus. I'll try to clarify...
– Brian H
1 hour ago
It wasn't an issue with all machines, but it was an issue which spread across many types of machines. On something like a VIC-20 or an Apple II, the memory system will always respond to a request by the time the CPU would be interested in the response. Conversely, on something like a 6502-based Nibbler arcade machine, ROM accesses were designed to have a wait state (although a machine used in competition had a broken wait-state circuit whose failure simply caused the game to run a little faster than normal, giving the player an unfair advantage).
– supercat
57 mins ago
There's an obvious reason for that, in that the Apple II and VIC-20 have CPUs running at 1MHz, while the RAM is faster. As such the CPU can access the RAM on without any wait states; it's even fast enough for the video hardware to have a go on alternate cycles usually without contention. Once you've got a CPU that's faster than its RAM, wait states are inevitable though.
– Matthew Barber
50 mins ago
There are small machines with wait states induced only by slow RAM — e.g. the Electron accesses ROM at 2Mhz but RAM at a max 1Mhz and forces delays to the CPU to deal with the latter. Does that count?
– Tommy
15 mins ago
I was referring to wait states introduced by DRAM latency, not contention with DMA devices sharing the bus. I'll try to clarify...
– Brian H
1 hour ago
I was referring to wait states introduced by DRAM latency, not contention with DMA devices sharing the bus. I'll try to clarify...
– Brian H
1 hour ago
It wasn't an issue with all machines, but it was an issue which spread across many types of machines. On something like a VIC-20 or an Apple II, the memory system will always respond to a request by the time the CPU would be interested in the response. Conversely, on something like a 6502-based Nibbler arcade machine, ROM accesses were designed to have a wait state (although a machine used in competition had a broken wait-state circuit whose failure simply caused the game to run a little faster than normal, giving the player an unfair advantage).
– supercat
57 mins ago
It wasn't an issue with all machines, but it was an issue which spread across many types of machines. On something like a VIC-20 or an Apple II, the memory system will always respond to a request by the time the CPU would be interested in the response. Conversely, on something like a 6502-based Nibbler arcade machine, ROM accesses were designed to have a wait state (although a machine used in competition had a broken wait-state circuit whose failure simply caused the game to run a little faster than normal, giving the player an unfair advantage).
– supercat
57 mins ago
There's an obvious reason for that, in that the Apple II and VIC-20 have CPUs running at 1MHz, while the RAM is faster. As such the CPU can access the RAM on without any wait states; it's even fast enough for the video hardware to have a go on alternate cycles usually without contention. Once you've got a CPU that's faster than its RAM, wait states are inevitable though.
– Matthew Barber
50 mins ago
There's an obvious reason for that, in that the Apple II and VIC-20 have CPUs running at 1MHz, while the RAM is faster. As such the CPU can access the RAM on without any wait states; it's even fast enough for the video hardware to have a go on alternate cycles usually without contention. Once you've got a CPU that's faster than its RAM, wait states are inevitable though.
– Matthew Barber
50 mins ago
There are small machines with wait states induced only by slow RAM — e.g. the Electron accesses ROM at 2Mhz but RAM at a max 1Mhz and forces delays to the CPU to deal with the latter. Does that count?
– Tommy
15 mins ago
There are small machines with wait states induced only by slow RAM — e.g. the Electron accesses ROM at 2Mhz but RAM at a max 1Mhz and forces delays to the CPU to deal with the latter. Does that count?
– Tommy
15 mins ago
add a comment |
The DRAM chips used for memory needed a certain memory access cycle length, for example 1000ns. Also CPUs needed several clock cycles to perform a memory cycle, so for example a 8086 could take 4 cycles to access memory. If the CPU is running at 5 MHz, the memory access takes only 800ns which is too fast for the memory. Therefore one wait state is needed to get 1000ns memory cycle. Lowering the CPU speed to 4 MHz would allow it to run with zero wait states. Basically wait states were needed because memory speeds were slower than what CPUs could access. Advertising does tell something about system performance. For example, if one system has 1000ns memories and another has 800ns memories, a 5 MHz 8086 is able to run at 0ws with faster memories and at 1ws with slower ones. In theory the 0ws machine can transfer data 25% more in same time than the 1ws machine can. Surely faster memories were more expensive so maybe it was important to advertise why two identical looking systems had a significant price difference.
add a comment |
The DRAM chips used for memory needed a certain memory access cycle length, for example 1000ns. Also CPUs needed several clock cycles to perform a memory cycle, so for example a 8086 could take 4 cycles to access memory. If the CPU is running at 5 MHz, the memory access takes only 800ns which is too fast for the memory. Therefore one wait state is needed to get 1000ns memory cycle. Lowering the CPU speed to 4 MHz would allow it to run with zero wait states. Basically wait states were needed because memory speeds were slower than what CPUs could access. Advertising does tell something about system performance. For example, if one system has 1000ns memories and another has 800ns memories, a 5 MHz 8086 is able to run at 0ws with faster memories and at 1ws with slower ones. In theory the 0ws machine can transfer data 25% more in same time than the 1ws machine can. Surely faster memories were more expensive so maybe it was important to advertise why two identical looking systems had a significant price difference.
add a comment |
The DRAM chips used for memory needed a certain memory access cycle length, for example 1000ns. Also CPUs needed several clock cycles to perform a memory cycle, so for example a 8086 could take 4 cycles to access memory. If the CPU is running at 5 MHz, the memory access takes only 800ns which is too fast for the memory. Therefore one wait state is needed to get 1000ns memory cycle. Lowering the CPU speed to 4 MHz would allow it to run with zero wait states. Basically wait states were needed because memory speeds were slower than what CPUs could access. Advertising does tell something about system performance. For example, if one system has 1000ns memories and another has 800ns memories, a 5 MHz 8086 is able to run at 0ws with faster memories and at 1ws with slower ones. In theory the 0ws machine can transfer data 25% more in same time than the 1ws machine can. Surely faster memories were more expensive so maybe it was important to advertise why two identical looking systems had a significant price difference.
The DRAM chips used for memory needed a certain memory access cycle length, for example 1000ns. Also CPUs needed several clock cycles to perform a memory cycle, so for example a 8086 could take 4 cycles to access memory. If the CPU is running at 5 MHz, the memory access takes only 800ns which is too fast for the memory. Therefore one wait state is needed to get 1000ns memory cycle. Lowering the CPU speed to 4 MHz would allow it to run with zero wait states. Basically wait states were needed because memory speeds were slower than what CPUs could access. Advertising does tell something about system performance. For example, if one system has 1000ns memories and another has 800ns memories, a 5 MHz 8086 is able to run at 0ws with faster memories and at 1ws with slower ones. In theory the 0ws machine can transfer data 25% more in same time than the 1ws machine can. Surely faster memories were more expensive so maybe it was important to advertise why two identical looking systems had a significant price difference.
answered 1 hour ago
JustmeJustme
4273
4273
add a comment |
add a comment |
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Brian, this question is rather wide. It's almost like asking why TTL chips need current and why don't they use all the same. It might be a good idea to narrow it a bit down.
– Raffzahn
2 hours ago
Many processors have had some notion of variable memory timing that can be configured one way or another. Some dynamically, some by data driven configuration, others by simply hard-coding one specific timing. See, for example, retrocomputing.stackexchange.com/questions/9562/…
– Erik Eidt
1 hour ago