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Modern CPUs employ a hierarchy of memory technologies. Registers, built into the chip have the lowest access times, but are expensive and volatile. Cache is a middle-man between RAM and registers to store data structures to reduce latency between RAM and registers. RAM holds, for the scope of this query, active program code and their data structures. Non-volatile storage is used by programs to save their data and hold the OS and its programs.

The latency of accessing data in memory has been a major bottleneck to creating faster CPUs that do not sit idle, awaiting further instruction. As such, various methods have been designed to parallelize workloads, CPUs to predict branching to hide memory access overhead, and more. However, the complexity of this has seemingly ignored another possibility: a whole-memory register file.

Such a CPU is built with 4, 8, 16, 32 GB or more, made of registers. No cache. No RAM. Just the CPU, the registers on the chip, and external non-volatile storage (SSD/Flash, HDD, etc.).

I understand that the demand for such a chip is unlikely to be sufficient to justify the cost, but I remain surprised that no one seems to have designed a simple device, such as a high-performance MCU or SoC with a small amount of register-only memory. Are there other (perhaps, engineering) challenges to the design and construction of such a chip?

EDIT to Clarify. I am not referring to a CPU in which all memory (DRAM technology) is integrated onto the CPU die, nor am I referring to a cache that is expanded to multiple Gigabytes. I am asking about a design in which the registers remain their existing technology... just expanded by a few orders of magnitude to be able to hold multiple gigabytes of data.

Two factors work against your idea:

• the optimal chip production processes for (D)RAM and logic (CPU) are different. Combining both on the same chip leads to compromises, and the result is far less optimal than what can be achieved with separate chips, each built with their own optimal process.




• fast memory (registers) takes more die area and consumes more current (energy) than slow memory. Consequently, when the CPU die is filled with really fast memory (CPU speed), the size of that memory would be nowhere near the GB's you mention. It would be more like the current sizes of the fastest on-chip caches.

There is insufficient room on the CPU die to fit such a vast amount of memory, current RAM memory relies on DIMMs with multiple chips.

The cost is also an issue, CPU die space is more expensive because of a different manufacturing process.

We currently have CPU caches (memory on the die) for this purpose and they are as big as possible. For most purposes there is no need to make this cache directly addressable.

Here is the die of an i7-5960X with a 20 MB L3 Cache:

source: https://www.anandtech.com/show/8426/the-intel-haswell-e-cpu-review-core-i7-5960x-i7-5930k-i7-5820k-tested

As you add more registers to a CPU, the access time gets slower and slower, because you need logic to pick say one of 1024 register instead of one of 16.

And registers are fast because they are connect directly to various things input and output of ALUs mostly). You can do that with 16 registers, not with 1024.

L1 cache is about as fast as registers, but loses speed because of the issues selecting the right data and transferring data. L1 cache also gets slower with size. And then there is cost, of course. Look at the prices of CPUs with 20MB of L3 cache; that lets you guess how much 64GB of L3 cache would be.

I think the main reason it hasn't been done is because the performance might not be improved as much as one would think.

1) A CPU with a huge register set would probably need to run at a lower clock rate than one with a smalle register set.

a) Memories are essentially very large muxes. The larger the mux the more transistors need to be involved to perform an access. The more transistors you need the slower its going to run either because there is more levels of logic or because there is more transistors connected to the same node (so higher capacitance). There is a reason that memories don't run at the same speed as CPU logic.

b) Implementing that much memory takes a lot of silicon space. It takes time for signals to physically propagate across a larger piece of silicon (routing delay). Just because its larger its unlikely that the device would be able to run at the same speed as a physically smaller CPU.

2) The binary encodings of the machine instructions would get a lot less efficient if you add more registers.
For example if your CPU has 4 registers then you need 2 bits to encode a register selection.
If your CPU has 4 billion 64-bit registers (making 32GB) then you need 32 bits to select each register.

Lets take for example an instruction that computes the logical OR of two registers and stores the result in a third register.

For a CPU having 4 registers you need to reserve 6 bits to encode the operand and destination selections.

For a CPU having 4 billion registers you need ot use 96 bits of operand space to encode the register selections.

Instructions that used to take 16 bits might now take 128 bits. The size of the programs would get a lot larger in terms of memory useage without necessarily adding to their functionality.

One could of course be clever and create some instruction encodings that just use the first X register locations to save bits. But then we are just back to the original register concept.





There are devices that have single cycle memory access but they are micro-controllers or system on a chip and typically have much lower clock rates than the CPU in a PC. They are usually limited to a few 10s to 100s of MHz for single cycle memory access. And even in those cases the memory sizes are usually not GB.

In some ways it depends what you mean by "registers". There are natural trade-offs between:

• Cost - fast access is more expensive


• Heat - fast access produces more heat


• Size - larger blocks of data are slower to access -- so even ignoring cost, you can't scale the registers bigger and expect them to keep the same speed, as you have to go and "get the data" from wherever it is stored on the chip.

One of the first CPUs, the Intel 4004, could be (and often was) used with no RAM, and had no cache, so the CPU you want exists (although it still used a ROM to store the program).